1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to a capacitor structure and a method for forming the same.
2. Description of the Related Art
Many state-of-the-art integrated circuits require the use of capacitors. For example, in dynamic random access memory (DRAM) devices, capacitors perform a vital data storing function. As DRAM and other memory devices become more highly integrated, new fabrication techniques are required to increase the storage capacity of these capacitors. It has become more difficult, however, to obtain the required capacitance levels. Adequate capacitance levels are important in obtaining proper device characteristics such as data retention, refresh effects, and constant operation characteristics.
To increase capacitance levels, the semiconductor industry has focused on developing capacitor electrodes having three-dimensional structures. This is because the capacitance of a capacitor is directly proportional to the surface area of the capacitor electrodes. Accordingly, fabrication technologies have been developed to increase the effective surface area by increasing the height of the cell capacitor electrode or storage node. FIG. 1, for example, is a graph showing the relationship between the height of the storage node with respect to a design rule according to the related art. As shown in FIG. 1, in the related art, as the design rule decreases, the storage node height increases.
Unfortunately, however, increasing the height of the storage node can result in several problems. For example, if the required height of the storage node is more than about 10,000 angstroms, it becomes very difficult to pattern conductive layers as storage nodes. Also, as the storage node height increases, the possibility of leaning storage nodes also increases significantly. Leaning storage nodes can result in an electrical bridge between adjacent storage nodes. This is partly illustrated in FIGS. 2 and 3. FIG. 2 is a graph schematically illustrating that as the height of the storage node increases, the CD (critical dimension) of the bottom storage node decreases. FIG. 3 is a photograph of conventional capacitor structures in a semiconductor device of the related art showing various storage nodes leaning toward adjacent storage nodes.
In addition to the problems identified above, as the design rule is decreased, problems with closed storage node contacts increase. FIG. 4 is a photograph showing a closed storage node contact, showing a “not open” phenomenon, in a conventional capacitor array of a semiconductor memory device according to the related art. Because of these and other problems, there remains a significant need for improved integrated circuit capacitors and methods of forming the same.